1. Field of the Invention
This invention relates to a semiconductor integrated circuit device such as a logic embedded memory having a logic circuit and a memory integrated in one chip.
2. Description of the Related Art
Recently, in a semiconductor integrated circuit device such as a logic embedded memory, as the integration density becomes higher, the capacity of the memory portion becomes larger. If a memory macro of a large capacity is formed in the logic embedded memory, it becomes difficult to receive/transmit a signal with respect to the logic circuit and the performance is deteriorated by distributing a clock in the memory macro. Therefore, a large number of memory macros of middle- or small-size capacities are arranged in many cases. For example, if a memory having a total capacity of 32 Mbits is required, four memory macros of 8 Mbits are formed.
Further, in the logic embedded memory, the requirement for the performance becomes severer and a setting value of an internal timer and voltage of an internal power supply of the memory macro configured by a DRAM can be finely tuned. Therefore, the setting value of the internal timer and voltage of the internal power supply are previously stored in a nonvolatile storage circuit such as fuses, ROM or the like. Since the arrangement of the nonvolatile storage circuit such as fuses, ROM or the like is limited in many respects, it is not provided in the memory macro but provided outside the memory macro and memory data is serially transferred to registers provided in the memory macro in the initialization sequence for startup of the power supply. Then, the setting value of the internal timer and the internal power supply voltage are tuned based on the data transferred to the registers (for example, refer to “Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy”, Micheal R, et al., IEEE2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE DIGEST pp. 191-194). At this time, in order to enhance the robustness of the data transfer operation, a receiving circuit which receives data read out from the memory circuit is provided and a complicated transfer protocol is used in some cases.
However, if a large number of memory macros of small capacities are formed, it is required to provide a large number of registers, internal timing setting circuits which set the setting values of the internal timers and internal voltage setting circuits which set the voltages of the internal power supplies in the memory macros. As a result, the pattern-occupied area becomes larger in comparison with a case wherein a small number of memory macros of large capacities are formed. In addition, if the data receiving circuit is provided in each memory macro, the pattern-occupied area is further increased.